This invention relates to improvements of a semiconductor memory and, more particularly, to a bit line circuit section of a static memory using MOS FETs (metal oxide semiconductor field effect transistors).
FIG. 1 shows an example of a prior-art bit line circuit section in one column of a memory cell array of the static type memory made of MOS FETs. BL and BL are a pair of bit lines. Memory cell MC (enclosed by a broken line) is a static memory cell. Actually, a plurality of memory cells MC are provided between a pair of bit lines BL and BL. However, only one of them is illustrated for simplicity. WL is a word line. Word lines WL are provided for memory cells, respectively. However, only one of them that is connected to memory cell MC illustrated, is shown for simplicity. Reference numeral 51 denotes a precharge/equalize circuit for precharging the bit lines and equalizing their potentials. Numeral 52 denotes a pull-up circuit for pulling up the voltages of the bit lines. Q6 and Q7 denote transistors for column selection. Numeral 53 represents a sense amplifier. Memory cell MC comprises a flip-flop and N channel transistors Q10 and Q11. The flip-flop includes transistors Q8 and Q9 as drivers, and high-resistance load resistors R1 and R2. Transistors Q10 and Q11 are transfer gates controlled by a word line select signal. The connection point of load resistor R1 and transistor Q8 and that of load resistor R2 and transistor Q9 form a pair of input/output nodes. One terminal of the source-drain path of transistor Q10 is contacted to the input/output node formed between load resistor R1 and transistor Q8. One terminal of the source-drain path of transistor Q11 is connected to the input/output node formed between load resistor R2 and transistor Q9. The other terminals of the source-drain path of transistors Q10 and Q11 are connected to bit lines BL and BL, respectively. Load resistor R1 and transistor Q8 are connected in series between power source potential V.sub.DD and ground potential V.sub.SS. Load resistor R2 and transistor Q9 are also connected in series between them.
The operation of the bit line circuit section taken when data is read out, will be described, referring to a timing chart shown in FIG. 2. Assuming that bit line precharge/equalize signal .phi.BPL is at an active level (in this example, V.sub.DD level), N channel transistors Q3, Q4 and Q5 of bit line precharge/equalize circuit 51 are turned on. Upon the turning-on of the transistors, the potentials of bit lines BL and BL are pulled up to voltage level (V.sub.DD -V.sub.TN) by transistors Q3 and Q4 as precharge loads. During the pull-up of voltage, the potential of these bit lines are equalized by equalizer transistor Q5. V.sub.DD is a power source potential. V.sub.TN is a threshold voltage of each N channel transistor. A word line is then selected, and the drive transistor being at the low potential of memory cell MC which is connected to selected word line WL, lowers the potential of the low potential bit line (in this case, BL). The potential of the low potential bit line is determined by the difference between the drive current for normally ON type transistor Q2 of bit line pull-up circuit 52 and the pull-in current of the low potential side of the cell and lowered to a mid level between V.sub.DD power potential and V.sub.SS ground potential. The high potential bit line (in this case, BL) remains almost unchanged at precharge potential (V.sub.DD -V.sub.TN), since transistor Q8 does not pull in any current. The potential change is therefore slight. This causes potential difference .DELTA.V between a pair of bit lines BL and BL. Based on the potential difference, data is detected by the sense amplifier 53. Normally ON type transistor Q2 is provided for preventing potential difference .DELTA.V from becoming so large that the operation of bit lines is slowed down.
In the prior-art static memory of FIG. 1, bit line pull-up transistors Q1 and Q2 and bit line precharge transistors Q3 and Q4 are at same threshold voltage V.sub.TN. Therefore, normally ON type transistor Q2 for bit line pull-up, which is connected to the low potential bit line (in this case, BL), is turned on. As the result of the turning-on of the transistor, a DC current flows through V.sub.DD power source node, bit line pull-up transistor Q2, low potential bit line BL, transistor Q11 as a transfer gate and transistor Q9 as a driver of selected MC, and V.sub.SS ground node in this order, as shown by the broken line in FIG. 1. This DC current replaces part of the pull-in current of the low potential side of memory cell MC. The pull-in current used for causing the potential difference .DELTA.V between the bit lines, is reduced. The speed of the increase of the potential difference .DELTA.V between the bit lines, is decreased. Therefore, the sense operation of the sense amplifier is slowed down. This leads to a problem that the read-out speed of the memory is decreased.